HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 437
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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14.1
This chip includes a four-channel direct memory access controller (DMAC). The DMAC can be
used in place of the CPU to perform high-speed transfers between external devices that have
DACK (transfer request acknowledge signal), external memory, memory-mapped external
devices, and on-chip supporting modules (SIOF, SCIF, USBF, A/D converter, and D/A converter).
Using the DMAC reduces the burden on the CPU and increases overall operating efficiency.
14.1.1
The DMAC has the following features.
• Four channels
• 4-GB physical address space
• Selectable data transfer length: 8-bit, 16-bit, 32-bit, or 16-byte transfer (In 16-byte transfer,
• Maximum of 16 M times of transfers (16777216 times)
• Address mode: Dual address mode and single address mode are supported. In addition, direct
• Channel functions: Transfer mode that can be specified is different in each channel.
four 32-bit reads are executed, followed by four 32-bit writes.)
address transfer mode or indirect address transfer mode can be selected.
⎯ Dual address mode transfer: Both the transfer source and transfer destination are accessed
⎯ Single address mode transfer: Either the transfer source or transfer destination peripheral
⎯ Channel 0: Can accept requests from peripheral modules and external requests.
⎯ Channel 1: Can accept requests from peripheral modules.
⎯ Channel 2: Can accept requests from peripheral modules. This channel has a source address
Section 14 Direct Memory Access Controller (DMAC)
by address. Dual address mode has direct address transfer mode and indirect address
transfer mode.
Direct address transfer mode: The values specified in the DMAC registers indicates the
transfer source and transfer destination. Two bus cycles are required for one data transfer.
Indirect address transfer mode: Data is transferred with the address stored prior to the
address specified in the transfer source address in the DMAC. Other operations are the
same as those of direct address transfer mode. This function is only valid in channel 3.
Four bus cycles are requested for one data transfer.
device is accessed (selected) by means of the DACK signal, and the other device is
accessed by address. One transfer unit of data is transferred in one bus cycle.
reload function, which reloads a source address for each 4 transfers.
Overview
Features
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 379 of 1036
REJ09B0254-0600
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