HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 237
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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7.3
7.3.1
Interrupt priority registers A to G (IPRA to IPRG) are 16-bit read/write registers that set priority
levels from 0 to 15 for on-chip supporting module, IRQ, and PINT interrupts. These registers are
initialized to H'0000 at power-on reset, and manual reset, but are not initialized in standby mode.
Table 7.7 lists the relationship between the interrupt sources and the IPRA to IPRG bits.
Table 7.7
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
Note: * Always read as 0. Only 0 should be written in.
As listed in table 7.7, four sets of on-chip supporting modules or IRQ or PINT interrupts are
assigned to each register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set
with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is
requested); H'F is priority level 15 (the highest level). A reset initializes IPRA to IPRG to H'0000.
Initial value:
Initial value:
INTC Registers
Interrupt Priority Registers A to G (IPRA to IPRG)
Interrupt Request Sources and IPRA to IPRG
R/W:
R/W:
Bit:
Bit:
Bits 15 to 12
TMU0
WDT
IRQ3
PINT0 to PINT7
DMAC
USBH
Reserved*
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
Bits 11 to 8
TMU1
REF
IRQ2
PINT8 to PINT15
Reserved*
LCDC
USBF0
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
Rev.6.00 Mar. 27, 2009 Page 179 of 1036
TMU2
SCI
IRQ1
IRQ5
SCIF
Bits 7 to 4
PCC0
USBF1
Section 7 Interrupt Controller (INTC)
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
Bits 3 to 0
RTC
Reserved*
IRQ0
IRQ4
ADC
SIOF
AFEIF
REJ09B0254-0600
R/W
R/W
9
0
1
0
R/W
R/W
8
0
0
0
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