HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 450

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
Bit 6—DREQ Select (DS): DS selects the sampling method of the DREQ pin that is used in
external request mode is detection in low level or at the falling edge.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Also, it should be cleared to 0 (low-level detection) if an on-chip supporting module is specified as
a transfer request source in channel 0.
Bit 6: DS
0
1
Bit 5—Transmit Mode (TM): TM specifies the bus mode when transferring data.
Bit 5: TM
0
1
Bits 4 and 3—Transmit Size 1, 0 (TS1 and TS0): TS1 and TS0 specify the size of data to be
transferred.
Bit 4: TS1
0
0
1
1
Bit 2—Interrupt Enable (IE): Setting this bit to 1 generates an interrupt request when the
number of times of data transfers specified with DMATCR has completed (TE = 1).
Bit 2: IE
0
1
Rev.6.00 Mar. 27, 2009 Page 392 of 1036
REJ09B0254-0600
Bit 3: TS0
0
1
0
1
Description
DREQ detected in low level
DREQ detected at falling edge
Description
Cycle steal mode
Burst mode
Description
Interrupt request is not generated even when data transfer ends by the
specified count
Interrupt request is generated when data transfer ends by the specified count
Description
Byte size (8 bits)
Word size (16 bits)
Longword size (32 bits)
16-byte unit (4 longword transfers)
(Initial value)
(Initial value)
(Initial value)
(Initial value)