HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 191

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Table 4.2
Exception
Type
Reset
General
exception
events
Current
Instruction
Aborted
Aborted
and retried
Completed
Exception Event Vectors
Exception Event
Power-on reset
Manual reset
H-UDI reset
CPU address error
(instruction access)
TLB miss
(instruction access
not in repeat loop)
TLB miss
(instruction access in
repeat loop) *
TLB invalid
(instruction access)
TLB protection
violation
(instruction access)
General illegal
instruction exception
Illegal slot instruction
exception
CPU address error
(data access)
TLB miss
(data access not in
repeat loop)
TLB miss
(data access in repeat
loop) *
TLB invalid (data
access)
TLB protection
violation
(data access)
Initial page write
Unconditional trap
(TRAPA instruction)
User breakpoint trap
DMA address error
4
4
Priority *
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Rev.6.00 Mar. 27, 2009 Page 133 of 1036
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10
12
Exception
Order
—
1
2
2
3
4
5
5
6
7
7
8
9
5
n *
2
Section 4 Exception Handling
Vector
Address
H'A0000000
H'A0000000
H’A0000000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REJ09B0254-0600
Vector Offset
—
—
—
H'00000100
H'00000400
H’00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100