HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 646

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.10 FIFO Data Count Set Register 2 (SCFDR2)
The SCFDR2 is a 16-bit register which indicates the number of data stored in the transmit FIFO
data register 2 (SCFTDR2) and the receive FIFO data register 2 (SCFRDR2). It indicates the
number of transmit data in the SCFTDR2 with the upper eight bits, and the number of receive data
in the SCFRDR2 with the lower eight bits. The SCFDR2 is always read from the CPU.
The SCFDR2 indicates the number of non-transmitted data stored in the SCFTDR2. The H'00
means no transmit data, and the H'10 means that the full of transmit data are stored in the
SCFTDR2.
The SCFDR2 indicates the number of receive data stored in the SCFRDR2. The H'00 means no
receive data, and the H'10 means that the full of receive data are stored in the SCFRDR2.
Rev.6.00 Mar. 27, 2009 Page 588 of 1036
REJ09B0254-0600
Upper 8 Bits:
Lower 8 Bits:
Initial value:
Initial value:
R/W:
R/W:
15
—
—
R
R
0
7
0
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
R4
12
T4
R
R
0
4
0
R3
T3
11
R
R
0
3
0
R2
T2
10
R
R
0
2
0
R1
T1
R
R
0
1
0
9
R0
T0
R
R
8
0
0
0