HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 703

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

(5) Transmit or Receive Reset
SIOF can reset independently the transmit and receive portions by setting 1 in the following bits.
• Transmit reset: (TXRST bit of SICTR register)
• Receive reset: (RXRST bit of SICTR register)
Table 20.11 shows the initialized contents by transmit or receive reset.
Table 20.11 Transmit or Receive Reset
Reset Type
Transmit reset
Receive reset
(6) Module Stop
SIOF stops transmit or receive operation with holding the contents of all registers at module stop.
Issue the transmit or receive reset, when the transmit or receive operation is not executed directly
after the module stop.
Initialized Register or Bits
SITDR register
Transmit FIFO write pointer
Transmit FIFO read pointer
TCRDY, TFEMP, and TDREQ bits in SISTR register
TXE bit in SICTR register
SIRDR register
Receive FIF0 write pointer
Receive FIF0 read pointer
RCRDY, RFFUL, and RDREQ bits in SISTR register
RXE bit in SICTR register
Rev.6.00 Mar. 27, 2009 Page 645 of 1036
Section 20 Serial IO (SIOF)
REJ09B0254-0600