HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 1040

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 32 Electrical Characteristics
32.3.11 SIOF Module Signal Timing
Table 32.14 SIOF Module Signal Timing
Conditions: V
Item
SIOMCLK clock input cycle time
SIOMCLK input high-level width
SIOMCLK input low-level width
SCK_SIO clock cycle time
SCK_SIO output high-level width
SCK_SIO output low-level width
SIOFSYNC output delay time
SCK_SIO input high-level width
SCK_SIO input low-level width
SIOFSYNC input setup time
SIOFSYNC input hold time
TXD_SIO output delay time
RXD_SIO input setup time
RXD_SIO input hold time
Note: t
Rev.6.00 Mar. 27, 2009 Page 982 of 1036
REJ09B0254-0600
PCYC
is the cycle time (ns) of the peripheral clock (Pφ)
CC
Q = 2.6 to 3.6 V, V
SIOMCLK
Figure 32.52 SIOMCLK Input Timing
CC
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MCYC
MWH
MWL
SICYC
SWHO
SWLO
FSD
SWHI
SWLI
FSS
FSH
STDD
SRDS
SRDH
= 1.60 to 2.05 V, AV
t
MWH
Min
30
0.4 × t
0.4 × t
2 × t
0.4 × t
0.4 × t
—
0.4 × t
0.4 × t
20
20
—
20
20
t
MCYC
PCYC
MCYC
MCYC
SICYC
SICYC
SICYC
SICYC
t
MWL
CC
= 3.3 ± 0.3 V, Ta = –20 to 75°C
Max
—
—
—
—
—
—
20
—
—
—
—
20
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
32.52
32.52
32.52
32.53 to 32.57
32.53 to 32.56
32.53 to 32.56
32.53 to 32.56
32.57
32.57
32.57
32.57
32.53 to 32.57
32.53 to 32.57
32.53 to 32.57