HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 230
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 7 Interrupt Controller (INTC)
when the RTC is not used, interruption by means of IRL interrupts cannot be performed in standby
mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt processing starts. Correct operation cannot be guaranteed if the level is not maintained.
However, the priority level can be changed to a higher one.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRL interrupt
processing.
7.2.4
PINT Interrupt
PINT interrupts are input by priority from pins PINT0 to PINT15 with a level. The priority level
can be set by priority setting registers D (IPRD) in a range from levels 0 to 15, in the unit of
PINT0 to PINT7 or PINT8 to PINT15.
The PINT interrupt level should be held until the interrupt is accepted and interrupt handling is
started.
The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by PINT interrupt
processing.
PINT interrupts can wake the chip up from the standby state when the relevant interrupt level is
higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator is used).
7.2.5
On-Chip Supporting Module Interrupts
On-chip supporting module interrupts are generated by the following fourteen modules:
• Timer unit (TMU)
• Realtime clock (RTC)
• Serial communication interface (SCI, SCIF)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• Direct memory access controller (DMAC)
• Analog-to-digital converter (ADC)
• PC Card controller (PCC)
• OHCI compliant USB HOST controller (USBH)
• USB function controller (USBF)
• AFE interface (AFEIF)
• LCD controller (LCDC)
Rev.6.00 Mar. 27, 2009 Page 172 of 1036
REJ09B0254-0600
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