HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 146

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 2 CPU
Table 2.32 DSP Operation Instructions
Instruction
DCT PADD Sx,Sy,Dz
DCF PADD Sx,Sy,Dz
DCT PSUB Sx,Sy,Dz
DCF PSUB Sx,Sy,Dz
DCT PSHA Sx,Sy,Dz
Rev.6.00 Mar. 27, 2009 Page 88 of 1036
REJ09B0254-0600
PMULS Se,Sf,Dg 111110**********
PADD Sx,Sy,Du
PMULS Se,Sf,Dg
PSUB Sx,Sy,Du
PMULS Se,Sf,Dg
PADD Sx,Sy,Dz
PSUB Sx,Sy,Dz
PSHA Sx,Sy,Dz
Instruction Code
0100eeff0000gg00
111110**********
0111eeffxxyygguu
111110**********
0110eeffxxyygguu
111110**********
10110001xxyyzzzz
111110**********
10110010xxyyzzzz
111110**********
10110011xxyyzzzz
111110**********
10100001xxyyzzzz
111110**********
10100010xxyyzzzz
111110**********
10100011xxyyzzzz
111110**********
1010001xxyyzzzz
111110**********
10010010xxyyzzzz
Operation
Se * Sf → Dg (signed)
Sx + Sy → Du
Se * Sf → Dg (signed)
Sy – Sy → Du
Se * Sf → Dg (signed)
Sx + Sy → Dz
If DC = 1, Sx + Sy → Dz
If DC = 0, nop
If DC = 0, Sx + Sy → Dz
If DC = 1, nop
Sx – Sy → Dz
If DC = 1, Sx – Sy → Dz
If DC = 0, nop
If DC = 0, Sx – Sy → Dz
If DC = 1, nop
If Sy > = 0, Sx << Sy → Dz
(arithmetic shift)
If Sy<0, Sx>>Sy → Dz
If DC = 1 & Sy > = 0,
Sx << Sy → Dz (arithmetic
shift)
If DC = 1 & Sy < 0,
Sx >> Sy → Dz
If DC = 0, nop
Execu-
tion
States
1
1
1
1
1
1
1
1
1
1
1
DC
—
*
*
*
*
*
*
*
*
*
*