HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 608

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 18 Smart Card Interface
The operating sequence is:
1. The data line is high impedance when not in use and is fixed high with a pull-up resistor.
2. The transmitting side starts one frame of data transmission. The data frame starts with a start
3. On the smart card interface, the data line returns to high impedance after this. The data line is
4. The receiving side checks parity. When the data is received normally with no parity errors, the
5. The transmitting side transmits the next frame of data unless it receives an error signal. If it
Rev.6.00 Mar. 27, 2009 Page 550 of 1036
REJ09B0254-0600
bit (Ds, low level). The start bit is followed by eight data bits (D0 to D7) and a parity bit (Dp).
pulled high with a pull-up resistor.
receiving side then waits to receive the next data. When a parity error occurs, the receiving
side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving
station returns the signal line to high impedance after outputting the error signal for a specified
period. The signal line is pulled high with a pull-up resistor.
does receive an error signal, it returns to step 2 to re-transmit the erroneous data.
D0 to D7:
With no parity error
With parity error
DE:
Dp:
Ds:
Ds
Ds
Start bit
Data bits
Parity bit
Error signal
D0
D0
Figure 18.3 Data Format for Smart Card Interface
D1
D1
Transmitting station output
Transmitting station output
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Dp
Dp
station output
Receiving
DE