HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 401

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

2. Self-Refreshing
Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are
generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE
bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low.
Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is
cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command
issuance is disabled for the number of cycles specified by the TPC bits in MCR. Self-refresh
timing is shown in figure 12.20. Settings must be made so that self-refresh clearing and data
retention are performed correctly, and auto-refreshing is performed at the correct intervals. When
self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby
mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and
RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-
CKIO,
CKIO2
CKE
CSn
RAS
CAS
RD/WR
Figure 12.19 Synchronous DRAM Auto-Refresh Timing
Tp
TRr
TRrw
Rev.6.00 Mar. 27, 2009 Page 343 of 1036
Section 12 Bus State Controller (BSC)
TRrw
(Tpc)
REJ09B0254-0600