HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 755

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

23.5.8
Together with USB interrupt flag register 0, USBIFR1 indicates interrupt status information
required by the application. When an interrupt source occurs, the corresponding bit is set to 1 and
an interrupt request is sent to the CPU according to the combination with USB interrupt enable
register 1. Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits.
Bits 7 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—USB Connect Status (VBUSMN): This bit is a status bit for monitoring the state of the
USBF_VBUS pin. It reflects the state of the USBF_VBUS pin.
Bit 2—EP3 Transfer Request (EP3 TR): This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is received from the host. A NACK handshake is
returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
Bit 1—EP3 Transmit Complete (EP3 TS): This bit is set when data is transmitted to the host
from endpoint 3 and an ACK handshake is returned.
Bit 0—USB Bus Connect (VBUSF): This bit is set to 1 when connecting to or disconnecting
from the USB bus. The USBF_VBUS pin is used to detect connection/disconnection.
The USBF_VBUS pin must be connected, as it is needed inside the module.
Initial value:
R/W:
USB Interrupt Flag Register 1 (USBIFR1)
Bit:
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
Rev.6.00 Mar. 27, 2009 Page 697 of 1036
VBUSMN
R
3
0
Section 23 USB Function Controller
EP3
R/W
TR
2
0
REJ09B0254-0600
EP3
R/W
TS
1
0
VBUSF
R/W
0
0