HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 164
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 3 Memory Management Unit (MMU)
Rev.6.00 Mar. 27, 2009 Page 106 of 1036
REJ09B0254-0600
Legend:
VPN (31−17) VPN (11−10) ASID SH SZ V
ASID: Address space identifier. Indicates the process that can access a virtual page. In single
VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of
PPN: Physical page number. Top 22 bits of physical address. PPN bits 11 and 10 are not used in
SH: Share status bit
PR: Set the most significant bit to 0.
SZ: Page-size bit
(15)
C: Cacheable bit. Indicates whether the page is cacheable.
D: Dirty bit. Indicates whether the page has been written to.
V: Valid bit. Indicates whether entry is valid.
virtual address for a 4-kbyte page. Since VPN bits 16 to 12 are used as the index number,
they are not stored in the TLB entry.
virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0,
the address is compared with the ASID in PTEH when address comparison is performed.
0 = Page not shared between processes
1 = Page shared between processes
0 = 1-kbyte page
1 = 4-kbyte page
0 = Invalid
1 = Valid
Cleared to 0 by a power-on reset. Not affected by a manual reset.
case of a 4-kbyte page. Attention must be paid to the synonym problem in case of a 1-kbyte
page (see section 3.4.4, Avoiding Synonym Problems).
Protection key field. 2-bit field encoded to define the access rights to the page.
00: Reading only is possible in privileged mode.
01: Reading/writing is possible in privileged mode.
10: Reading only is possible in privileged/user mode.
11: Reading/writing is possible in privileged/user mode.
0 = Non-cacheable
1 = Cacheable
0 = Not written to
1 = Written to
31
31
Figure 3.5 Logical Address and TLB Structure
(2)
Virtual address (1-kbyte page)
Virtual address (4-kbyte page)
VPN
(8)
VPN
(1)
TLB entry
(1)
(1)
12
10
11
9
Offset
PPN
(22)
Offset
0
0
PR
(2)
(1) (1)
C D
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