HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 630

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.5
The serial mode register 2 (SCSMR2) is an eight-bit register that specifies the SCIF serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR2. The SCSMR2 is initialized to H'00 by a reset or
in standby and module standby modes.
Bit 7—Reserved: This bit always read 0. The write value should always be 0.
Bit 6—Character Length (CHR): Selects seven-bit or eight-bit data in the asynchronous mode.
Bit 6: CHR
0
1
Note: * When seven-bit data is selected, the MSB (bit 7) of the transmit FIFO data register 2 is not
Bit 5—Parity Enable (PE): Selects whether or not to add a parity bit to transmit data and to
check the parity of receive data.
Bit 5: PE
0
1
Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition
and check. The O/E setting is ignored when parity addition and check is disabled.
Rev.6.00 Mar. 27, 2009 Page 572 of 1036
REJ09B0254-0600
Initial value:
transmitted.
Serial Mode Register 2 (SCSMR2)
R/W:
Bit:
Description
Eight-bit data.
Seven-bit data. *
Description
Parity bit not added or checked.
Parity bit added and checked.
When PE is set to 1, an even or odd parity bit is added to transmit data,
depending on the parity mode (O/E) setting. Receive data parity is checked
according to the even/odd (O/E) mode setting.
—
R
7
0
CHR
R/W
6
0
R/W
PE
5
0
R/W
O/E
4
0
STOP
R/W
3
0
—
R
2
0
CKS1
R/W
0
1
(Initial value)
(Initial value)
CKS0
R/W
0
0