HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 374

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 12 Bus State Controller (BSC)
12.3
12.3.1
This LSI supports both big endian, in which the 0 address is the most significant byte in the byte
data, and little endian, in which the 0 address is the least significant byte. This switchover is
designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-on reset,
big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus
widths (word and long word) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word. This means data alignment is done by matching the device's data width and endian.
The access unit must also be matched to the device's bus width. This also means that when
longword data is read from a byte-width device, the read operation must happen 4 times. In this
LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 12.6 to 12.11 show the relationship between endian, device data width, and access unit.
Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment
Operation
Byte access
at 0
Byte access
at 1
Byte access
at 2
Byte access
at 3
Word access
at 0
Word access
at 2
Longword
access at 0
Rev.6.00 Mar. 27, 2009 Page 316 of 1036
REJ09B0254-0600
BSC Operation
Endian/Access Size and Data Alignment
D31 to
D24
Data
7 to 0
—
—
—
Data
15 to 8
—
Data
31 to 24
D23 to
D16
—
Data
7 to 0
—
—
Data
7 to 0
—
Data
23 to 16
Data Bus
D15 to
D8
—
—
Data
7 to 0
—
—
Data
15 to 8
Data
15 to 8
D7 to
D0
—
—
—
Data
7 to 0
—
Data
7 to 0
Data
7 to 0
WE3,
DQMUU
Assert
Assert
Assert
WE2,
DQMUL
Assert
Assert
Assert
Strobe Signals
WE1,
DQMLU
Assert
Assert
Assert
WE0,
DQMLL
Assert
Assert
Assert