HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 495

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Compare-Match Flag Clear Timing
The CMF bit in the CMCSR0 register is cleared by writing 0 to the bit after reading 1. Figure
14.30 shows the timing when the CMF bit is cleared by the CPU.
Peripheral clock
match signal
input clock
Peripheral clock
CMCOR0
CMCNT0
CMCNT0
Compare
Figure 14.30 Timing of CMF Clear by the CPU
CMF
(Pφ)
CMI
Figure 14.29 Timing of CMF Setting
CMF
(Pφ)
N
N
Section 14 Direct Memory Access Controller (DMAC)
CMCSR0 write cycle
T
Rev.6.00 Mar. 27, 2009 Page 437 of 1036
1
T
2
0
REJ09B0254-0600