HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 918

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 28 A/D Converter
28.1.4
Table 28.2 summarizes the A/D converter’s registers.
Table 28.2 A/D Converter Registers
Name
A/D data register A (high)
A/D data register A (low)
A/D data register B (high)
A/D data register B (low)
A/D data register C (high)
A/D data register C (low)
A/D data register D (high)
A/D data register D (low)
A/D control/status register
A/D control register
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
Rev.6.00 Mar. 27, 2009 Page 860 of 1036
REJ09B0254-0600
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Only 0 can be written to bit 7, to clear the flag.
2. When address translation by the MMU does not apply, the address in parentheses
Register Configuration
should be used.
Abbreviation
ADDRAH
ADDRAL
ADDRBH
ADDRBL
ADDRCH
ADDRCL
ADDRDH
ADDRDL
ADCSR
ADCR
R/W
R
R
R
R
R
R
R
R
R/(W) *
R/W
1
Initial Value Address
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'07
H'04000080
H'04000082
H'04000084
H'04000086
H'04000088
H'0400008A
H'0400008C
H'0400008E
H'04000092
(H'A4000080) *
(H'A4000082) *
(H'A4000084) *
(H'A4000086) *
(H'A4000088) *
(H'A400008A) *
(H'A400008C) *
(H'A400008E) *
H'04000090
(H'A4000090) *
(H'A4000092) *
2
2
2
2
2
2
2
2
2
2
Access size
16, 8
8
16, 8
8
16, 8
8
16, 8
8
8
8