HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 469

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

DMAC indirect
address buffer
Internal data
address bus
DMAC data
D31 to D0
A25 to A0
Internal
buffer
(Transfer between External Memories, External Memory with 16-bit Width)
WEn
CSn
bus
RD
CK
Figure 14.10 Example of Transfer Timing in Indirect Address Mode
Notes: 1. The internal address bus value does not change, and controlled by the port.
Transfer source
address (H)
(1st)
Transfer source
Transfer between external memories (external memories is 16-bit bus width)
2. The DMAC does not fetch the value until 32-bit data is output to the internal
Address read cycle
address (H)
address *
Indirect
data bus.
1
Transfer source
address (L)
(2nd)
Transfer source
address (L)
address *
NOP
Indirect
Section 14 Direct Memory Access Controller (DMAC)
2
cycle
NOP
NOP
Indirect address
Rev.6.00 Mar. 27, 2009 Page 411 of 1036
Indirect
address
Indirect address
read cycle
(3rd)
Data
Transfer data
Transfer
data
Transfer data
nation address
Transfer desti-
write cycle
Data
REJ09B0254-0600
(4th)
Transfer
Transfer
data
data