HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 217

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Specify the entry address for selecting the entry (bits 11 to 4), L indicating the longword position
within the (16-byte) line (bits 3 and 2: 00 is longword 0, 01 is longword 1, 10 is longword 2, and
11 is longword 3), W for selecting the way (bits 12 and 11: in normal mode, 00 is way 0, 01 is
way 1, 10 is way 2, and 11 is way 3), and H'F1 to indicate data array access (bits 31 to 24).
Both reading and writing use the longword of the data array specified by the entry address, way
number and longword address. The access size of the data array is fixed at longword.
1. Address array access
2. Data array access (both read and write accesses)
X: 0 for read, don't care for write
*: Don't care bit
Address specification
Address specification
Data specification
Data specification
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access
Read access
Write access
0 0 0
31
31
31 30 29
31
31
1111 0000
1111 0000
1111 0001
24
24
24
Address tag (31−10)
23
23
23
* ………… *
* ………… *
* ………… *
14
14
14
13
13
13
Longword
W
W
W
12
12
12
11
11
10
11
Rev.6.00 Mar. 27, 2009 Page 159 of 1036
Entry
Entry
Entry
9
LRU
4
4
4
4
3
3
3
3
A
0
X
L
REJ09B0254-0600
X
2
*
2
*
2
Section 5 Cache
2
1
0
0
0
1
U
0
0
0
V
0
0
0
0
0