HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 313
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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9.7.3
The timings of each pin in hardware standby mode are shown in figures 9.10 and 9.11.
CA pin is sampled by EXTAL2 (32.768 kHz). Hardware standby request is detected when two
continuous cycles go low in this clock.
Keep CA pin low during hardware standby mode.
The clock starts oscillation when the CA pin is set high after setting the RESETP pin low.
Notes: 1. Reset: HH (STATUS1 is high, STATUS0 is high)
Timing of Hardware Standby Mode
RESETP
CKIO, CKIO2
CA
STATUS
2. Standby: LH (STATUS1 is low, STATUS0 is high)
3. Normal: LL (STATUS1 is low, STATUS0 is low)
4. Bcyc: Bus clock cycle
5. Rcyc: EXTAL2 (32.768 kHz) clock cycle
6. CKIO2 can be used at only clock modes 0,1 and 2.
7. Undefined
*6
Figure 9.10 Hardware Standby Mode Timing
(CA = Low in Normal Operation)
2 Rcyc or more
Normal
*3
Section 9 Power-Down Modes and Software Reset
*5
Standby
Rev.6.00 Mar. 27, 2009 Page 255 of 1036
*2
0−10Bcyc
*7
*4
Reset
REJ09B0254-0600
*1
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