HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 182

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 3 Memory Management Unit (MMU)
3.6
In order for TLB operations to be managed by software, TLB contents can be read or written to in
the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the logical
address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000 to
H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000 to
H'F3FFFFFF. The V bit in the address array can also be accessed from the data array. Only
longword access is possible for both the address array and the data array.
Rev.6.00 Mar. 27, 2009 Page 124 of 1036
REJ09B0254-0600
(4) 4 or more instructions repeated (inst1, inst2, ..., instN, SR.RC=2)
inst-1
inst0
inst1
inst2
instN-3
instN-2
instN-1
instN
inst1
inst2
instN-3
instN-2
instN-1
instN
instN+1
:
:
Memory-Mapped TLB
IF
ID
IF
EX MA WB
ID
IF
Figure 3.14 MMU Exception in Repeat Loop (cont)
: Exception source stage where SPC is not correct
EX MA WB
ID
IF
and repeat loop can not be restarted
EX MA WB
ID
EX MA WB
IF
ID
IF
:
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
EX MA WB
IF
ID
IF
:
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
EX MA WB