HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 454

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
14.2.6
Note: * Only a write of 0 after a read of 1 is enabled for the AE and NMIF bits.
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMAC
transfer mode.
This register is initialized to 0 by a power-on reset. The previous values are held in standby mode.
Bits 15 to 10—Reserved: These bits are always read as 0 and should only be written with 0.
Bits 9 and 8—Priority Mode 1, 0 (PR1 and PR0): PR1 and PR0 select the priority level between
channels when transfer requests are generated for multiple channels simultaneously.
Bit 9: PR1
0
1
Bits 7 to 3—Reserved: These bits are always read as 0 and should only be written with 0.
Rev.6.00 Mar. 27, 2009 Page 396 of 1036
REJ09B0254-0600
Initial value:
Initial value:
DMA Operation Register (DMAOR)
R/W:
R/W:
Bit:
Bit:
Bit 8: PR0
0
1
0
1
15
—
—
R
R
0
7
0
14
—
—
R
R
0
6
0
Description
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
Round-robin
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
11
—
—
R
R
0
3
0
R/(W)*
AE
10
—
R
0
2
0
R/(W)*
NMIF
PR1
R/W
0
0
9
1
(Initial value)
DME
PR0
R/W
R/W
8
0
0
0