HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 693

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Monaural or stereo of transmit data is set with TDLE bit and TDRE bit of SILTDAR register. To
choose monaural or stereo for receive, RDLE bit and RDRE bit of SIRDAR register must be set.
The same sound for right and left in transmit data is set with TLREP bit of SITDAR register.
Table 20.6 shows establishment of sound mode for transmit data, table 20.7 shows establishment
of sound mode for receive data, use only the left channel in case of monaural 8 bits transfer.
Table 20.6 Transmit Data Sound Mode
Mode
Monaural
Stereo
Same sound for right and left
Table 20.7 Receive Data Sound Mode
Mode
Monaural
Stereo
Note: Same mode for right and left don’t exist in receive data.
TDLE
1
1
1
RDLE
1
1
Rev.6.00 Mar. 27, 2009 Page 635 of 1036
TDRE
0
1
1
Bit
Bit
RDRE
0
1
Section 20 Serial IO (SIOF)
TLREP
*
0
1
REJ09B0254-0600
*: Don’t care