HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 92

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 2 CPU
other than A0G and A1G in the word mode, lower half of the register is cleared. When it is A0 or
A1, the data is sign-extended to bits 39 to 32 and lower half of it is cleared. When A0G or A1G is
a destination register in the word mode, data is loaded into 8-bit register, but A0 or A1 is not
cleared. In the longword mode, when a destination register is A0 or A1, it is sign-extended to bits
39 to 32.
Tables 2.3 and 2.4 show the data type of registers used in the DSP instructions. Some instructions
cannot use some registers shown in the tables because of instruction code limitation. For example,
PMULS can use A1 for source registers, but cannot use A0. These tables ignore details of the
register selectability.
Table 2.3
A0, A1
A0G, A1G
X0, X1
Y0, Y1
M0, M1
Rev.6.00 Mar. 27, 2009 Page 34 of 1036
REJ09B0254-0600
Registers
Destination Register of DSP Instructions
Data
transfer
transfer
DSP
Data
transfer
DSP
Data
Instructions
Fixed-point, PSHA,
PMULS
Integer, PDMSB
Logical, PSHL
MOVS.W
MOVS.L
MOVS.W
MOVS.L
Fixed-point, PSHA,
PMULS
Integer, logical,
PDMSB, PSHL
MOVX/Y.W, MOVS.W
MOVS.L
39
Sign-extended 40-bit result
Sign-extended 24-bit result
Cleared
Sign-extended 16-bit data
Sign-extended 32-bit data
Data
Data
Guard Bits
32 31
16-bit result
No update
No update
32-bit result
16-bit result
16-bit result
32-bit data
Register Bits
16 15
Cleared
Cleared
Cleared
Cleared
Cleared
0