HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 48

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Figure 30.2 Continuous 32-MB Area Mode .............................................................................. 889
Figure 30.3 Continuous 16-MB Area Mode (Area 6)................................................................ 890
Figure 30.4 SH7727 Interface.................................................................................................... 903
Figure 30.5 PCMCIA Memory Card Interface Basic Timing ................................................... 907
Figure 30.6 PCMCIA Memory Card Interface Wait Timing..................................................... 908
Figure 30.7 PCMCIA I/O Card Interface Basic Timing............................................................ 909
Figure 30.8 PCMCIA I/O Card Interface Wait Timing ............................................................. 910
Figure 30.9 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. 911
Section 31 User-Debugging Interface (H-UDI)
Figure 31.1 H-UDI Block Diagram ........................................................................................... 916
Figure 31.2 TAP Controller State Transitions ........................................................................... 925
Figure 31.3 H-UDI Reset........................................................................................................... 927
Section 32 Electrical Characteristics
Figure 32.1 Power-On Sequence ............................................................................................... 930
Figure 32.2 Power Supply Voltage and Operating Frequency .................................................. 935
Figure 32.3 EXTAL Clock Input Timing .................................................................................. 941
Figure 32.4 CKIO Clock Input Timing ..................................................................................... 941
Figure 32.5 CKIO Clock Output Timing................................................................................... 942
Figure 32.6 Power-on Oscillation Settling Time ....................................................................... 942
Figure 32.7 Oscillation Settling Time at Standby Return (Return by Reset)............................. 943
Figure 32.8 Oscillation Settling Time at Standby Return (Return by NMI).............................. 943
Figure 32.9 Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0)............... 944
Figure 32.10 PLL Synchronization Settling Time by Reset or NMI Interrupt ............................ 944
Figure 32.11 PLL Synchronization Settling Time by IRQ/IRL and PINT0/1 Interrupt .............. 945
Figure 32.12 PLL Sync Stabilization Time at Frequency Multiplier Factor Change .................. 945
Figure 32.13 Reset Input Timing................................................................................................. 947
Figure 32.14 Interrupt signal Input Timing ................................................................................. 947
Figure 32.15 Bus Release Timing ............................................................................................... 948
Figure 32.16 Pin Drive Timing at Standby.................................................................................. 948
Figure 32.17 Basic Bus Cycle (No Wait) .................................................................................... 951
Figure 32.18 Basic Bus Cycle (One Wait) .................................................................................. 952
Figure 32.19 Basic Bus Cycle (External Wait, WAITSEL = 1) .................................................. 953
Figure 32.20 Burst ROM Bus Cycle (No Wait) .......................................................................... 954
Figure 32.21 Burst ROM Bus Cycle (Two Waits) ...................................................................... 955
Figure 32.22 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ........................................ 956
Figure 32.23 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)..... 957
Figure 32.24 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1)..... 958
Figure 32.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4),
RCD = 0, CAS Latency = 1, TPC = 1) ................................................................... 959
Rev.6.00 Mar. 27, 2009 Page xlvi of lvi
REJ09B0254-0600

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