HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 673

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 15—Control Command Data Channel 0 Enable (CD0E)
Bit 15: CD0E
0
1
Bits 11 to 8—Control Command Data Assignment for Channel 0 (CD0A3 to CD0A0): The
slot assignment for control channel 0 in transmit and receive frames is specified from 0000(0:
initial value) to 1110(14) by this register. The receive data for control channel 0 is set in bits
SITC05 to SITC00 of SIRCR register. The receive data for control channel 0 is stored in bits
SIRC015 to SIRC00 in SIRCR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits CD0A3 to CD0A0.
Bit 7—Control Command Data Channel 1 Enable (CD1E)
Bit 7: CD1E
0
1
Bits 3 to 0—Control Command Data Assignment for Channel 1 (CD1A3 to CD1A0): The slot
assignment for control channel 1 in transmit and receive frames is specified from 0000(0: initial
value) to 1110(14) by this register. The receive data for control channel 1 is set in bits SIRC115 to
SIRC10 of SIRCR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits CD1A3 to CD1A0.
Description
Disable transmitting or receiving of control command of channel 0.
Enable transmitting or receiving of control command of channel 0.
Description
Disable transmitting or receiving of control command of channel 1.
Enable transmitting or receiving of control command of channel 1.
Rev.6.00 Mar. 27, 2009 Page 615 of 1036
Section 20 Serial IO (SIOF)
REJ09B0254-0600
(Initial value)
(Initial value)