HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 297

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Bit 2: MSTP5
0
1
Bit 1—Module Stop 4 (MSTP4): Specifies halting the clock supply to the serial communication
interface SCI (SCIF) with FIFO. When the MSTP4 bit is set to 1, the clock supply to the SCIF is
halted
Bit 1: MSTP4
0
1
Bit 0— Reserved: This bit is always read as 0. The write value should always as 0.
9.2.3
The standby control register 3 (STBCR3) is an 8-bit readable/writable register that controls
standby operation for the on-chip supporting modules. STBCR3 is initialized to H'00 by a power-
on reset.
Bit 7— Module Stop 17 (MSTP17): Specifies halting the clock supply to the serial IO with FIFO
interface (SIOF). When the MSTP17 bit is set to 1, the clock supply to the serial IO with FIFO
interface (SIOF) is halted.
Bit 7: MSTP17
0
1
Bit 6— Reserved: This bit is always read as 0. The write value should always as 0.
Initial value:
Standby Control Register 3 (STBCR3)
R/W:
Bit:
MSTP17
Description
ADC runs
Clock supply to ADC halted, and all registers initialized
Description
SCIF runs
Clock supply to SCI2 (SCIF) halted
Description
SIOF runs
Clock supply to SIOF halted
R/W
7
0
R/W
6
0
MSTP15 MSTP14 MSTP13
R/W
5
0
Section 9 Power-Down Modes and Software Reset
R/W
4
0
Rev.6.00 Mar. 27, 2009 Page 239 of 1036
R/W
3
0
R/W
2
0
MSTP11 MSTP10
REJ09B0254-0600
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
R/W
0
0

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