HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 186
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 3 Memory Management Unit (MMU)
3.7
1. Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction,
2. The value of the RC bit in MMUCR may be set abnormally if all of the following conditions
Rev.6.00 Mar. 27, 2009 Page 128 of 1036
REJ09B0254-0600
(1) MMU is on (AT is set to 1 in MMUCR).
(2) Identical entries in the TLB address array reference the same VPN using multiple ways.
(3) A TLB related exception occurs.
The VPN is not initialized at power on reset or manual reset. Therefore, identical entries may
access two or more VPNs using the same value. In such cases, certain entries in the TLB
address array may end up as shown below if, for example, they are registered in way 3.
In this case way 0 and way 3 reference the same VPN, thereby satisfying condition (2).
The above conditions can also be satisfied by TLB handling in software. For example, the
situation shown below could occur if, after invalidating way 0 (by setting V from 1 to 0) for an
entry in the TLB address array, the entry is registered to way 3. In this case as well, the same
VPN is assigned for both way 0 and way 3, thereby satisfying condition (2) above.
LDC @Rm+, SR instruction, and RTE instruction) and the following instruction, or the
LDTLB instruction, should be used with the TLB disabled or in a fixed physical address
space (the P1 or P2 space).
are met:
After reset
WAY VPN
0
3
After invalidation of way 0
WAY VPN
0
3
Usage Notes
12345
12345
12345
11111
V
0
0
V
0
0
After registration to way 3
WAY VPN
0
3
WAY VPN
0
3
After registration to way 3
12345
12345
12345
12345
V
0
1
V
0
1
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