HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 467

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
(2) In the indirect address transfer mode
The address of the memory in which data to be transferred is stored is specified in the transfer
source address register (SAR3) in the DMAC. 16-byte transfer is not provided in this mode.
The address value specified in the transfer source address register in the DMAC is read first,
and this value is temporarily stored in the DMAC. Next, the read value is output as an address,
and data on that address is stored in in the DMAC again. Then, the value read afterwards is
written to the address specified by the transfer destination address register; thus one DMA
transfer is completed.
Figure 14.9 shows an example of this operation. In this example, the transfer destination,
transfer source, and storage destination of the indirect address are all in external memories, and
the transfer data size is 16 or 8 bits. Figure 14.10 shows an example of the transfer timing.
In this mode, one NOP cycle (CK1 cycle shown in figure 14.10) is required to output data
which was read as an indirect address to an address bus.
For a 32-bit data transfer, third and fourth bus cycles shown in figure 14.10 are required twice
for each; a total of six bus cycles and one NOP cycle are required.
Rev.6.00 Mar. 27, 2009 Page 409 of 1036
REJ09B0254-0600