HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 11

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

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Figure 12.17 Basic Timing for Synchronous
DRAM Single Write
RAS3
Figure 12.19 Synchronous DRAM Auto-
Refresh Timing
RAS3
Figure 12.20 Synchronous DRAM Self-
Refresh Timing
RAS3
Figure 12.21 Synchronous DRAM Mode
Write Timing
RAS3
14.1 Overview
This chip includes a four-channel direct
memory access controller (DMAC). The
DMAC can be used in place of the CPU to
perform high-speed transfers between
external devices that have DACK (transfer
request acknowledge signal), external
memory, memory-mapped external
devices, and on-chip supporting modules
(SIOF, SCIF, USB function, and A/D
converter). Using the DMAC reduces the
burden on the CPU and increases overall
operating efficiency
14.6 Usage Notes
5. The on-chip supporting modules that the
DMAC can access are, SIOF, SCIF, USB
function, A/D converter, and I/O ports. Do
not access the other on-chip supporting
modules by the DMAC.
16.1.3 Pin Configuration
Table 16.1 RTC Pin Configuration
Notes: 1. When the RTC is not used, set
EXTAL2 to pull-up (to Vcc) and make no
connection for XTAL2.
Section 17 Serial Communication Interface
(SCI)
TxD, RxD, SCK
Section 18 Smart Card Interface
TxD, RxD, SCK
Previous Version
RAS
RAS
RAS
RAS
This chip includes a four-channel direct
memory access controller (DMAC). The
DMAC can be used in place of the CPU to
perform high-speed transfers between
external devices that have DACK (transfer
request acknowledge signal), external
memory, memory-mapped external
devices, and on-chip supporting modules
(SIOF, SCIF, USBF, A/D converter, and
D/A converter). Using the DMAC reduces
the burden on the CPU and increases
overall operating efficiency
5. The on-chip supporting modules that the
DMAC can access are, SIOF, SCIF, USBF,
A/D converter, D/A converter, and I/O ports.
Do not access the other on-chip supporting
modules by the DMAC.
Notes: 1. When the RTC is not used, set
EXTAL2 to pull-up (to Vcc-RTC) and make
no connection for XTAL2.
TxD0, RxD0, SCK0
TxD0, RxD0, SCK0
Rev.6.00 Mar. 27, 2009 Page ix of lvi
Revised Version
REJ09B0254-0600