HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 795

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 24 USB HOST Module
24.2.5
HcInterruptEnable
HcInterrutpEnable Register (H'04000410)
Each enable bit in the HcInterruptEnable register corresponds to the related interrupt bit in the
HcInterruptStatus register. The HcInterruptEnable register is used to control an event to generate a
hardware interrupt. A hardware interrupt is requested in the host bus when a bit in the
HcInterruptEnable register is set, a corresponding bit in the HcInteruptEnable register is set, and
the MasterInterrupEnable bit is set. As a result, the USBHI bit in Interrupt Request Register 3
(IRR3) of Interrupt Controller INTC is set (the USBHI bit is used in common regardless of the
content of the interrupt generation event). Therefore, the USBHI bit can be used when an interrupt
generation is detected by HCD.
Writing 1 in this register sets the corresponding bit, while writing 0 leaves the bit. When read, the
current value of this register is returned.
Rev.6.00 Mar. 27, 2009 Page 737 of 1036
REJ09B0254-0600