HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 847
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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25.2.19 LCDC Control Register (LDCNTR)
LDCNTR specifies start and stop of display by the LDCD.
Bits 15 to 1—Reserved
Bit 4— Display start auxiliary bit (DON2): Specifies the start of display operation using LCDC.
LCDC operation cannot be guaranteed if 0 is written to this bit at any time other than the start of
display operation. Note that a 1 written to this bit is automatically cleared to 0, so it is not
necessary to write 0 to it in order to clear it.
Bit 0—Display On (DON): Specifies the start and stop of the LCDC display operation.
The control sequence state can be checked by referencing the LPS value in bit 0 of the LCDC
power management mode register (LDPMMR).
Bit 4
DON2
0
1
Starting LCDC Display Operation (DON2 and DON bits change from B'00 to B'11):
1. Start LCDC operation.
2. Turn on the LCD module following the sequence set in the LCDC power management mode
Stopping LCDC Display Operation (DON2 and DON bits change from B'01 to B'00):
1. Turn off the LCD module following the sequence set in the LCDC power management mode
2. Stop LCDC operation.
Initial value:
register (LDPMMR) and LCDC control register (LDCNTR).
The sequence ends when the LPS value changes from B'00 to B'11.
Do not make any action to the DON bit until the sequence ends.
register (LDPMMR) and LCDC control register (LDCNTR).
The sequence ends when the LPS value changes from B'11 to B'00.
Do not make any action to the DON bit until the sequence ends.
R/W:
Bit:
15
—
R
0
Bit 0
DON
0
1
14
—
R
0
13
—
R
0
Description
Display-off mode: LCDC is stopped
Display-on mode: LCDC operates
12
—
R
0
11
—
R
0
10
—
R
0
—
R
9
0
—
R
8
0
Rev.6.00 Mar. 27, 2009 Page 789 of 1036
—
R
7
0
—
R
6
0
—
R
5
0
Section 25 LCD Controller
DON2
R/W
4
0
—
R
3
0
(Initial value)
REJ09B0254-0600
—
R
2
0
—
R
1
0
DON
R/W
0
0
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