HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 497

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

The state in the DMAC differ depending on the address reload function setting as shown in table
14.9.
Table 14.9 DMAC Sate after the Fourth Transfer Ends
Items
SAR
DAR
DMATCR
Bus right
DMAC operation
Interrupt
Transfer request source flag
clear
Notes: 1. When the value in DMATCR reaches 0 and the IE bit in CHCR has been set to 1,
14.5.2
In this example, DMA transfer is performed between the external memory specified with the
indirect address (transfer source) and the SCIF transmitter (transfer destination) using DMAC
channel 3. Table 14.10 shows the transfer conditions and register settings. In addition, it is
recommendable that the trigger for the number of transmit FIFO data is set to 1 (TTRG1 = TTRG0
= 1 in SCFCR).
2. When the value in DMATCR reaches 0, the transfer request source flag is cleared
3. Specify the burst mode when using the address reload function. This function may not
4. Set the DMATCR value to a multiple of four when using the address reload function.
Example of DMA Transfer between External Memory and SCIF Transmitter
(Indirect Address on)
interrupts are generated regardless of the address reload function setting.
regardless of the address reload function setting.
be correctly executed in the cycle steal mode.
This function may not be correctly executed if other values are specified.
Address Reload On
H'04000080
H'003FFFFC
H'0000007C
Released
Stops
Not generated
Executed
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 439 of 1036
Address Reload Off
H'04000090
H'003FFFFC
H'0000007C
Held
Continues operating
Not generated
Not executed
REJ09B0254-0600