HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 290

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 8 User Break Controller
4. The change of a UBC register value is executed in MA (memory access) stage. Therefore,
5. Notes in specifying the instruction during repeat execution with repeat instruction as the break
6. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR
7. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as
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REJ09B0254-0600
even if the break condition matches in the instruction fetch address following the instruction in
which the pre-execution break is specified as the break condition, no break occurs. In order to
know the timing UBC register is changed, read the last written register. Instructions after then
are valid for the newly written register value.
condition are as follows: When the instruction during repeat execution is specified as the break
condition,
(1) The break is not issued during repeat execution, which has fewer than three instructions.
(2) When the execution times break is set, no instruction fetch from memory occurs during
are read.
follows:
(1) Break and instruction fetch exceptions: Instruction fetch exception occurs first.
(2) Break before execution and operand exception: Break before execution occurs first.
(3) Break after execution and operand exception: Operand exception occurs first.
repeat execution under three instructions. Therefore, the execution times register BETR is
not decreased.