HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 835

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

25.2.8
LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette
memory is being used for display operation, display mode should be selected. When the palette
memory is being written to, CPU access mode should be selected.
Bits 15 to 5 and 3 to 1—Reserved
Bit 4—Palette State (PALS): Indicates the access right state of the palette.
Bit 4
PALS
0
1
Bit 0—Palette Read/Write Enable (PALEN): Controls CPU accesses to the palette.
Bit 0
PALEN
0
1
Initial value:
R/W:
Bit:
LCDC Palette Control Register (LDPALCR)
15
—
R
0
Description
Description
Display mode: LCDC uses the palette
CPU access mode: The host (CPU) uses the palette
Display mode: LCDC uses the palette
CPU access mode: The host (CPU) uses the palette
14
—
R
0
13
—
R
0
12
—
R
0
11
—
R
0
10
—
R
0
—
R
9
0
—
R
8
0
Rev.6.00 Mar. 27, 2009 Page 777 of 1036
—
R
0
7
—
R
6
0
—
R
5
0
Section 25 LCD Controller
PALS
R
4
0
—
R
3
0
REJ09B0254-0600
—
R
2
0
(Initial value)
(Initial value)
—
R
1
0
PALEN
R/W
0
0