HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 315

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

10.1
The on-chip oscillation circuits consist of the clock pulse generator (CPG) and watchdog timer
(WDT).
The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down
modes.
The watchdog timer (WDT) is a single-channel timer that counts the clock settling time and is
used when clearing standby mode and temporary standby, such as frequency changes. It can also
be used as an ordinary watchdog timer or interval timer.
10.1.1
The CPG has the following features:
• Four clock modes: Selection of four clock modes for different frequency ranges, power
• Three clocks generated independently: An internal clock for the CPU, cache, and TLB (Iφ); a
• Frequency change function: Internal and peripheral clock frequencies can be changed
• Power-down mode control: The clock can be stopped for sleep mode and standby mode and
consumption, direct crystal input, and external clock input.
peripheral clock (Pφ) for the on-chip supporting modules; and a bus clock (CKIO) for the
external bus interface.
independently using the PLL circuit and divider circuit within the CPG. Frequencies are
changed by software using frequency control register (FRQCR) settings.
specific modules can be stopped using the module standby function.
Overview
Features
Section 10 On-Chip Oscillation Circuits
Rev.6.00 Mar. 27, 2009 Page 257 of 1036
Section 10 On-Chip Oscillation Circuits
REJ09B0254-0600