HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 241

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Bits 5 and 4—IRQ2 Sense Select (IRQ21S and IRQ20S): Select whether the interrupt signal to
the IRQ2 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 5: IRQ21S
0
1
Bits 3 and 2—IRQ1 Sense Select (IRQ11S and IRQ10S): Select whether the interrupt signal to
the IRQ1 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 3: IRQ11S
0
1
Bits 1 and 0—IRQ0 Sense Select (IRQ01S and IRQ00S): Select whether the interrupt signal to
the IRQ0 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 1: IRQ01S
0
1
Bit 4: IRQ20S
0
1
0
1
Bit 2: IRQ10S
0
1
0
1
Bit 0: IRQ00S
0
1
0
1
Description
An interrupt request is detected at IRQ2 input falling edge
An interrupt request is detected at IRQ2 input rising edge
An interrupt request is detected at IRQ2 input low level
Reserved
Description
An interrupt request is detected at IRQ1 input falling edge
An interrupt request is detected at IRQ1 input rising edge
An interrupt request is detected at IRQ1 input low level
Reserved
Description
An interrupt request is detected at IRQ0 input falling edge
An interrupt request is detected at IRQ0 input rising edge
An interrupt request is detected at IRQ0 input low level
Reserved
Rev.6.00 Mar. 27, 2009 Page 183 of 1036
Section 7 Interrupt Controller (INTC)
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)

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