HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 698

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
Table 20.10 Receive Request Submit Condition
RFWM2 to RFWM0
000
100
101
110
111
When the data area or empty area exceed the above stage number, FIFO capacity always can be
used 16 stages. Therefore, over flow or under flow error are submitted when the data area, or
empty area excesses 16 stages.
Even if FIFO is not empty or full, the transmit request is cancelled when the above conditions
become not to be satisfied.
(3) Showing of Stage Number
The state of using transmit or receive FIFO is displayed in the following registers.
• Transmit FIFO: Shows stage number of empty area to bits TFUA4 to TFUA0 in SIFCTR
• Receive FIFO: Shows stage number of effective data to bits RFUA4 to RFUA0 of SIFCTR
The above contents show the number of data which CPU or DMAC can transfer.
Rev.6.00 Mar. 27, 2009 Page 640 of 1036
REJ09B0254-0600
register
register
Request Stage
Number
1
4
8
12
16
Receive Request Submit
Over 1 stage effective area
Over 4 stages effective area
Over 8 stages effective area
Over 12 stages effective area
16 stages effective area
Used Area
Small
Large