HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 686

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
20.2.12 Transmit Control Data Register (SITCR)
This register sets the transmit control data for SIOF. Setting to this register is effective when 1***
is set to FL bit of SIMDR register. This register is initialized at power on reset, software reset, or
transmit reset.
Bits 31 to 16—Transmit Control Data for Channel 0 (SITC015 to SITC00): These bits stores
data to be transfer as transmit control channel 0 data from TXD_SIO. The position of control data
for channel 0 is determined by the setting of CD0A bit of SICDAR register.
This bit is effective when 1 is set to CD0E bit of SICDAR register.
Bits 15 to 0—SIOF Transmit Control Data for Channel 1 (SITC115 to SITC10): These bits
stores data to be transfer as transmit control channel 1 command from TXD_SIO. The position of
control data for channel 1 is determined by the setting of CD1A bit of SICDAR register.
This bit is effective when 1 is set to CD1E bit of SICDAR register.
Rev.6.00 Mar. 27, 2009 Page 628 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SITC0
SITC1
R/W
R/W
31
15
15
15
0
0
SITC0
SITC1
R/W
R/W
30
14
14
14
0
0
SITC0
SITC1
R/W
R/W
29
13
13
13
0
0
SITC0
SITC1
R/W
R/W
28
12
12
12
0
0
SITC0
SITC1
R/W
R/W
27
11
11
11
0
0
SITC0
SITC1
R/W
R/W
26
10
10
10
0
0
SITC0
SITC1
R/W
R/W
25
9
0
9
9
0
SITC0
SITC1
R/W
R/W
24
8
0
8
8
0
SITC0
SITC1
R/W
R/W
23
7
0
7
7
0
SITC0
SITC1
R/W
R/W
22
6
0
6
6
0
SITC0
SITC1
R/W
R/W
21
5
0
5
5
0
SITC0
SITC1
R/W
R/W
20
4
0
4
4
0
SITC0
SITC1
R/W
R/W
19
3
0
3
3
0
SITC0
SITC1
R/W
R/W
18
2
0
2
2
0
SITC0
SITC1
R/W
R/W
17
1
0
1
1
0
SITC0
SITC1
R/W
R/W
16
0
0
0
0
0