HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 263

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

8.1.3
Table 8.1
Name
Break address register A
Break address mask
register A
Break bus cycle register A
Break address register B
Break address mask
register B
Break bus cycle register B
Break data register B
Break data mask register B
Break control register
Execution count break
register
Branch source register
Branch destination register
Break ASID register A
Break ASID register B
Notes: 1. Initialized by power-on reset. Values held in standby state and undefined by manual
2. Bit 31 of BRSR and BRDR (valid flag) is initialized by power-on resets. But other bits
Register Configuration
resets.
are not initialized.
Register Configuration
Abbr.
BARA
BAMRA
BBRA
BARB
BAMRB
BBRB
BDRB
BDMRB
BRCR
BETR
BRSR
BRDR
BASRA
BASRB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
H'00000000
H'00000000
Undefined *
Initial
Value *
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'0000
H'00000000
H'0000
Undefined *
Undefined
Undefined
Rev.6.00 Mar. 27, 2009 Page 205 of 1036
1
2
2
Address
H'FFFFFFB0
H'FFFFFFB4
H'FFFFFFB8
H'FFFFFFA0
H'FFFFFFA4
H'FFFFFFA8
H'FFFFFF90
H'FFFFFF94
H'FFFFFF98
H'FFFFFF9C 16
H'FFFFFFAC 32
H'FFFFFFBC 32
H'FFFFFFE4
H'FFFFFFE8
Section 8 User Break Controller
Access
Size
32
32
16
32
32
16
32
32
32
8
8
REJ09B0254-0600
CCN
CCN
Location
UBC
UBC
UBC
UBC
UBC
UBC
UBC
UBC
UBC
UBC
UBC
UBC