HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 496
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 14 Direct Memory Access Controller (DMAC)
14.5
14.5.1
In this example, DMA transfer is performed between the on-chip A/D converter (transfer source)
and the external memory (transfer destination) with the address reload function on. Table 14.8
shows the transfer conditions and register settings.
Table 14.8 Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Transfer Conditions
Transfer source: on-chip A/D converter
Transfer destination: external memory
Number of transfers: 128 (reloading 32 times)
Transfer source address: incremented
Transfer destination address: decremented
Transfer request source: A/D converter
Bus mode: burst
Transfer unit: long word
Interrupt request generated at end of transfer
Channel priority order: 0 > 2 > 3 > 1
When the address reload function is turned on, the value set in SAR returns to the initially set
value at each four transfers. In this example, when an interrupt request is generated from the AD
converter, longword data is read from the register in address H'04000080 of the A/D converter,
and the data is written to external memory address H'00400000. Since longword data has been
transferred, the values in SAR and DAR are H'04000084 and H'003FFFFC, respectively. The bus
right is retained and data transfers are successively performed because this transfer is in the burst
mode.
After four transfers end, fifth and sixth transfers are performed when the address reload function is
turned off, and the value in SAR is incremented by 4, such as H'0400008C, H'04000090,
H'04000094,.... When the address reload function is on, the DMA transfer stops after the fourth
transfer ends and the bus request signal to the CPU is cleared. At this time, the value stored in
SAR is not incremented from H'0400008C to H'04000090, but returns to the initially set value
H'04000080. The value in DAR continues being incremented regardless of the address reload
function setting.
Rev.6.00 Mar. 27, 2009 Page 438 of 1036
REJ09B0254-0600
Examples for Use
Example of DMA Transfer between A/D Converter and External Memory
(Address Reload on)
Converter and External Memory
SAR2
DMATCR2
CHCR2
Register
DAR2
DMAOR
Setting
H'04000080
H'00400000
H'00000080
H'00089E35
H'0101
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