HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 446

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
Bit 20—Direct/Indirect Selection (DI): DI selects direct address mode operation or indirect
address mode operation for a channel 3 source address.
This bit is only valid in CHCR3. This bit in CHCR0 to CHCR2 is always read as 0 and should
only be written with 0.
When using 16-byte transfer, direct address mode must be specified. Operation is not guaranteed if
indirect address mode is specified.
Bit 20: DI
0
1
Bit 19—Source Address Reload (RO): RO selects whether the source address initial value is
reloaded in channel 2.
This bit is only valid in CHCR2. This bit in CHCR0, CHCR1, and CHCR3 is always read as 0
and should only be written with 0.
When using 16-byte transfer, this bit must be cleared to 0, specifying non-reloading. Operation is
not guaranteed if reloading is specified.
Bit 19: RO
0
1
Bit 18—Request Check Level (RL): RL specifies the DRAK (acknowledge of DREQ) signal
output is high active or low active.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 18: RL
0
1
Rev.6.00 Mar. 27, 2009 Page 388 of 1036
REJ09B0254-0600
Description
Direct address mode
Indirect address mode
Description
A source address is not reloaded
A source address is reloaded
Description
Low-active output of DRAK
High-active output of DRAK
(Initial value)
(Initial value)
(Initial value)