HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 363

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
For Synchronous DRAM Interface: (see table 12.12)
Bit6:
AMX3
1
0
Values other than above
Notes: 1. Can only be set when using a 16-bit bus width.
2. Can only be set when using a 32-bit bus width.
Bit5:
AMX2
1
1
0
Bit 4:
AMX1
0
1
0
1
0
Bit 3:
AMX0
1
0
0
1
0
1
0
Description
The row address begins with A11 when bus width is 32 bit.
(The A10 value is output at A1 when the row address is
output. 4M × 16-bit × 4-bank products)
(The A11 value is output at A1 when the row address is
output. 8M × 16-bit × 4-bank products) *
The row address begins with A10 when bus width is 32 bit.
(The A9 value is output at A1 when the row address is
output. 1M × 16-bit × 4-bank products)
The row address begins with A11 when bus width is 32 bit.
(The A10 value is output at A1 when the row address is
output. 2M × 16-bit × 4-bank products)
(The A11 value is output at A1 when the row address is
output. 2M × 16-bit × 4-bank products)
The row address begins with A10 when bus width is 32 bit.
(The A9 value is output at A1 when the row address is
output. 512K × 32-bit × 4-bank products)
accessing synchronous DRAM memory.
The row address begins with A10 when bus width is 16 bit.
The row address begins with A11 when bus width is 16 bit.
The row address begins with A9 when bus width is 16 bit.
The row address begins with A10 when bus width is 16 bit.
The row address begins with A11 when bus width is 32 bit. *
The row address begins with A9 when bus width is 16 bit.
Reserved. AMX3 to AMX0 must be set to *1*** before
Reserved (illegal setting)
Rev.6.00 Mar. 27, 2009 Page 305 of 1036
Section 12 Bus State Controller (BSC)
1
REJ09B0254-0600
(Initial value)
2

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