HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 623
![SH3-DSP, LEAD FREE](/photos/28/62/286203/240-bfqfp__prqp0240kc-b_sml.jpg)
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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19.1
This LSI has one-channel serial communication interface with FIFO (SCIF) that supports
asynchronous serial communication. It also has 16-stage FIFO registers for both transfer and
receive that enables this LSI efficient high-speed continuous communication.
19.1.1
• Asynchronous serial communication:
• Full duplex communication: The transmitting and receiving sections are independent, so the
• On-chip baud rate generator with selectable bit rates
• Internal transmit/receive clock source
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
• On-chip modem control functions (RTS2 and CTS2)
⎯ Serial data communications are performed by start-stop in character units. The SCI can
⎯ Data length: Seven or eight bits
⎯ Stop bit length: One or two bits
⎯ Parity: Even, odd, or none
⎯ Receive error detection: Parity and framing errors
⎯ Break detection: Break is detected when the receive data next the generated framing error
SCI can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
receive-error interrupts are requested independently. The direct memory access controller
(DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receive-
FIFO-data-full interrupt.
power.
Section 19 Serial Communication Interface with FIFO
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
is the space 0 level and has the framing error. It is also detected by reading the RxD2 level
directly from the port SC data register (SCPDR) when a framing error occurs
Overview
Features
Section 19 Serial Communication Interface with FIFO (SCIF)
(SCIF)
Rev.6.00 Mar. 27, 2009 Page 565 of 1036
REJ09B0254-0600
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