HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 567

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
17.3
17.3.1
For serial communication, the SCI has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses.
Asynchronous/clock synchronous mode and the transmission format are selected in the serial
mode register (SCSMR), as listed in table 17.9. The SCI clock source is selected by the
combination of the C/A bit in the serial mode register (SCSMR) and the CKE1 and CKE0 bits in
the serial control register (SCSCR), as listed in table 17.10.
Asynchronous Mode:
• Data length is selectable: seven or eight bits.
• Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The
• In receiving, it is possible to detect framing errors, parity errors, overrun errors and breaks.
• An internal or external clock can be selected as the SCI clock source.
Clock Synchronous Mode:
• The transmission/reception format has a fixed eight-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.
combination of the preceding selections constitutes the communication format and character
length.
⎯ When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
⎯ When an external clock is selected, the external clock input must have a frequency 16 times
⎯ When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
⎯ When an external clock is selected, the SCI operates on the input synchronous clock. The
and can output a serial clock signal with a frequency matching the bit rate.
the bit rate. (The on-chip baud rate generator is not used.)
and outputs a synchronous clock signal to external devices.
on-chip baud rate generator is not used.
Operation
Overview
Section 17 Serial Communication Interface (SCI)
Rev.6.00 Mar. 27, 2009 Page 509 of 1036
REJ09B0254-0600

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