HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 147

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Instruction
DCF PSHA Sx,Sy,Dz
DCT PSHL Sx,Sy,Dz
DCF PSHL Sx,Sy,Dz
DCT
DCT
DCF
DCF
PSHL Sx,Sy,Dz
PCOPY Sx,Dz
PCOPY Sy,Dz
PCOPY Sx,Dz
PCOPY Sy,Dz
PCOPY Sx,Dz
PCOPY Sy,Dz
PDMSB Sx,Dz
PDMSB Sy,Dz
Instruction Code
111110**********
10010011xxyyzzzz
111110**********
10000001xxyyzzzz
111110**********
10000010xxyyzzzz
111110**********
10000011xxyyzzzz
111110**********
11011001xx00zzzz
111110**********
1111100100yyzzzz
111110**********
11011010xx00zzzz
111110**********
1111101000yyzzzz
111110**********
11011011xx00zzzz
111110**********
1111101100yyzzzz
111110**********
10011101xx00zzzz
111110**********
1011110100yyzzzz
If DC = 0 & Sy > = 0,
Sx << Sy → Dz (arithmetic
shift)
If DC = 0 & Sy < 0,
Sx >> Sy → Dz
If DC = 1, nop
If Sy > = 0, Sx << Sy → Dz
(logical shift)
If Sy < 0, Sx >> Sy → Dz
If DC = 1 & Sy > = 0,
Sx << Sy → Dz (logical shift)
If DC = 1 & Sy < 0,
Sx >> Sy → Dz
If DC = 0, nop
If DC = 0 & Sy > = 0,
Sx << Sy → Dz (logical shift)
If DC = 0 & Sy < 0,
Sx >> Sy → Dz
If DC = 1, nop
Sx → Dz
Sy → Dz
If DC = 1, Sx → Dz
If DC = 0, nop
If DC = 1, Sy → Dz
If DC = 0, nop
If DC = 0, Sx → Dz
If DC = 1, nop
If DC = 0, Sy → Dz
If DC = 1, nop
Sx → Dz normalization count
shift value
Sx → Dz normalization count
shift value
Operation
Rev.6.00 Mar. 27, 2009 Page 89 of 1036
REJ09B0254-0600
Execu-
tion
States
1
1
1
1
1
1
1
1
1
1
1
1
Section 2 CPU
DC
*
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*
*
*
*
*
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