HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 303

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

9.4.2
Standby mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module interrupt or
PINT) or a reset.
Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects
an NMI, IRL, IRQ, PINT *
the clock will be supplied to the entire chip and standby mode canceled after the time set in the
WDT’s timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low.
Interrupt exception handling then begins and a code corresponding to the interrupt source is set in
the INTEVT and INTEVT2 registers. After branching to the interrupt processing routine occurs,
clear the STBY bit in the STBCR register. The WTCNT stops automatically. If the STBY bit is
not cleared, WTCNT continues operation and transits to the standby mode *
This function prevents the data from being destroyed due to a rising voltage under an unstable
power supply. Interrupts are accepted during standby mode even when the BL bit in the SR
register is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP instruction.
Immediately after an interrupt is detected, the phase of the clock output of the CKIO and CKIO2
pin may be unstable, until the standby mode is canceled. The canceling condition is that the
interrupt request level (IRQ, IRL, or on-chip supporting module interrupt) is higher than the mask
level in the I3 to I0 bits in the SR register.
Notes: 1. When the RTC is being used, standby mode can be canceled using IRL3 to IRL0, IRQ4
2. Standby mode can be canceled with an RTC or TMU (only when running on the RTC
3. Use a power-on reset to cancel standby mode.
Canceling Standby Mode
to IRQ0 or PINT0 to PINT5.
clock) interrupt.
Operation is not guaranteed in the case of a manual reset or interrupt input.
1
, or on-chip supporting module (except the interval timer) *
Section 9 Power-Down Modes and Software Reset
Rev.6.00 Mar. 27, 2009 Page 245 of 1036
3
when it reaches H’80.
REJ09B0254-0600
2
interrupt,