HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 628

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2
19.2.1
The receive shift register 2 (SCRSR2) receives serial data. Data input at the RxD2 pin is loaded
into the SCRSR2 in the order received, LSB (bit 0) first, converting the data to parallel form.
When one byte has been received, it is automatically transferred to the SCFRDR2, which is a
receive FIFO data register 2. The CPU cannot read or write the SCRSR2 directly.
19.2.2
The 16-byte receive FIFO data register 2 (SCFRDR2) stores serial receive data. The SCIF
completes the reception of one byte of serial data by moving the received data from the receive
shift register 2 (SCRSR2) into the SCFRDR2 for storage. Continuous receive is enabled until 16
bytes are stored.
The CPU can read but not write the SCFRDR2. When data is read without received data in the
SCFRDR2, the value is undefined. When the received data in this register becomes full, the
subsequent serial data is lost.
Rev.6.00 Mar. 27, 2009 Page 570 of 1036
REJ09B0254-0600
Register Descriptions
Receive Shift Register 2 (SCRSR2)
Receive FIFO Data Register 2 (SCFRDR2)
R/W:
R/W:
Bit:
Bit:
—
R
7
7
—
R
6
6
—
R
5
5
—
R
4
4
—
R
3
3
—
R
2
2
—
R
1
1
—
R
0
0