HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 282

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 8 User Break Controller
8.3.4
1. The break condition on X/Y-memory bus cycle is specified only in channel B. If XYE in
2. When X-memory address is selected as the break condition, specify X-memory address in
8.3.5
1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break
2. In sequential break specification, internal/X/Y bus can be selected and the execution times
8.3.6
The PC when a break occurs is saved to the SPC in user breaks. The PC value saved is as follows
depending on the type of break.
1. When instruction fetch (before instruction execution) is specified as a break condition:
2. When instruction fetch (after instruction execution) is specified as a break condition:
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BBRB is set to 1, break address and break data on X/Y-memory bus are selected. At this time,
select X-memory bus or Y-memory bus by specifying XYS in BBRB. The Break condition
cannot include both X-memory and Y-memory at the same time. The break condition is
applied to X/Y-memory bus cycle by specifying CPU/data access/read or write/word or no
operand size specification in the break bus cycle register B (BBRB).
upper 16 bits in BARB and BAMRB. When Y-memory address is selected, specify Y-memory
address in lower 16 bits. Specification of X/Y-memory data is the same for BDRB and
BDMRB.
condition matches after channel A break condition matches. A user break is ignored even if
channel B break condition matches before channel A break condition matches. When channels
A and B condition match at the same time, the sequential break is not issued.
break condition can be also specified. For example, when the execution times break condition
is specified, the break condition is satisfied at channel B condition match with BETR = H'0001
after channel A condition match.
The value of the program counter (PC) saved is the address of the instruction that matches the
break condition. The fetched instruction is not executed, and a break occurs before it.
The PC value saved is the address of the instruction to be executed following the instruction in
which the break condition matches. The fetched instruction is executed, and a break occurs
before the execution of the next instruction.
Sequential Break
Value of Saved Program Counter
Break on X/Y-Memory Bus Cycle