HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 572
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 17 Serial Communication Interface (SCI)
Rev.6.00 Mar. 27, 2009 Page 514 of 1036
REJ09B0254-0600
Clear TE and RE bits in SCSCR to 0
Set CKE1 and CKE0 bits in SCSCR
Also set RIE, TIE, TEIE, and MPIE
Set TE or RE in SCSCR to 1.
Select transmit/receive
(TE and RE bits are 0)
Set value to SCBRR
format in SCSMR
interval elapsed?
as necessary.
Has a 1-bit
Initialize
End
Figure 17.7 Sample SCI Initialization Flowchart
Yes
Wait
No
(1)
(2)
(3)
(4)
(1) Select the clock source in the serial
(2) Select the communication format in
(3) Write the value corresponding to
(4) Wait at least one bit interval, then
control register (SCSCR). Leave
RIE, TIE, TEIE, MPIE, TE, and RE
cleared to 0. If clock output is
selected in asynchronous mode,
clock output starts immediately
after the setting is made to SCSCR.
the serial mode register (SCSMR).
the bit rate in the bit rate register
(SCBRR) unless an external clock
is used.
set TE or RE in the serial control
register (SCSCR) to 1. Also set
RIE, TIE, TEIE, and MPIE as
necessary. Setting TE and RE
enables the TxD0 and RxD0 pins to
be used. The initial states are the
mark transmit state, and the idle
receive state (waiting for a start bit).
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